Introduction to Computer Architecture
Welcome to one of the most exciting topics in Digital Technology: Computer Architecture! Have you ever wondered what actually happens inside your computer, smartphone, or tablet when you click a mouse, tap an app, or play a video game? At the heart of every digital device lies the Central Processing Unit (CPU), often called the "brain" of the computer.
In this chapter, we will open the hood of the computer to explore how hardware components interact to process instructions billions of times every single second. Don't worry if this seems a bit technical at first—we will break down every single concept into simple, bite-sized pieces with everyday analogies.
What you will learn:
• The fundamentals of the Von Neumann Architecture and the stored program concept.
• The core internal components of the CPU (the CU, ALU, and dedicated Registers).
• The three essential System Buses and how they transport signals.
• The step-by-step journey of the Fetch-Decode-Execute (F-D-E) Cycle.
• Key hardware factors that determine how fast a processor runs.
1. The Von Neumann Architecture
In the early days of computing, computers were designed to do only one specific task. If you wanted the computer to do something different, engineers had to physically rewire the whole machine! In 1945, mathematician and physicist John von Neumann introduced a revolutionary design known as the Stored Program Concept.
The Stored Program Concept
Under the Von Neumann model:
1. Data and Program Instructions are stored together in the same shared primary memory (RAM).
2. Instructions are fetched from memory, decoded, and executed serially (one after another) by the CPU.
Everyday Analogy: Imagine a single notebook. On page 1, you write a recipe (instructions: "add flour, crack egg, mix"). On page 2, you write down your grocery quantities (data: "200g, 2 eggs"). In the Von Neumann architecture, both the instructions on what to do and the actual values used are kept in the same memory book.
Key Features of Von Neumann Architecture
• A single Central Processing Unit (CPU) containing a Control Unit (CU) and an Arithmetic Logic Unit (ALU).
• A shared Memory Unit (RAM) for holding both data and instructions.
• Input and Output (I/O) interfaces to communicate with the outside world.
• Internal high-speed storage locations called Registers.
• A set of shared connection pathways called Buses.
Key Takeaway: The Von Neumann architecture revolutionized computing by allowing programs to be easily loaded and changed in memory without rewiring hardware.
2. Inside the CPU: Core Components
The CPU contains three main elements that work together seamlessly: the Control Unit, the Arithmetic Logic Unit, and special storage areas called Registers.
A. The Control Unit (CU)
The Control Unit is the manager or conductor of the CPU orchestra. It does not perform mathematical calculations itself; instead, it coordinates all activities inside the CPU and between other hardware devices.
Key responsibilities of the CU:
• It manages the Fetch-Decode-Execute cycle.
• It decodes instructions to determine what actions need to occur.
• It sends control signals to synchronize hardware operations (like reading from or writing to memory).
• It manages the internal clock signals.
B. The Arithmetic Logic Unit (ALU)
The ALU is the computer's calculator and logic engine. Whenever an instruction involves doing math or making a decision, the ALU takes over.
The ALU handles two types of operations:
• Arithmetic operations: Basic math such as addition (\(+\)), subtraction (\(-\)), multiplication (\(\times\)), and division (\(\div\)).
• Logical operations: Comparisons and Boolean logic checks, such as testing if two numbers are equal (\(A = B\)), checking inequalities (\(A > B\)), or performing \(AND\), \(OR\), and \(NOT\) operations.
C. Dedicated Registers
Registers are extremely small, ultra-fast temporary storage locations located directly inside the CPU chip. They hold memory addresses, instructions, or intermediate data that the CPU needs immediately.
Think of RAM as a large bookshelf across the room, while Registers are your hands holding the open page right in front of your eyes.
You need to know the following five core registers:
1. Program Counter (PC):
Holds the memory address of the next instruction waiting to be fetched and executed. After the address is copied, the PC automatically increments by \(1\) (\(PC = PC + 1\)) to point to the next instruction in sequence.
2. Memory Address Register (MAR):
Holds the memory address currently being accessed. This could be the location in RAM from which an instruction/data is being read, or the address where data is about to be written.
3. Memory Data Register (MDR):
(Sometimes called the Memory Buffer Register or MBR)
Holds the actual data or instruction that has just been fetched from RAM, or data that is waiting to be written out to RAM.
4. Current Instruction Register (CIR):
Holds the instruction that has just been fetched from memory while it is being decoded and executed by the Control Unit. The instruction is split into an Opcode (what operation to do) and an Operand (the data or address to do it on).
5. Accumulator (ACC):
A general-purpose working register associated directly with the ALU. It temporarily holds the intermediate results of arithmetic and logical calculations.
Memory Aid (Mnemonic):
Remember P-M-M-C-A: Please Make My Computer Awesome!
(PC \(\rightarrow\) MAR \(\rightarrow\) MDR \(\rightarrow\) CIR \(\rightarrow\) ACC)
Key Takeaway: The CU directs traffic, the ALU does math and logic decisions, and Registers provide lightning-fast scratchpad memory for the CPU.
3. System Buses
How do signals move between the CPU, RAM, and Input/Output devices? They travel along parallel wires called Buses. Together, these form the System Bus.
1. The Address Bus
• Purpose: Carries memory addresses from the CPU to RAM or I/O controllers, indicating where data should be read from or written to.
• Direction: Unidirectional (one-way only, from CPU to Memory).
• Bus Width: The number of parallel lines determines how many distinct memory locations the CPU can address. For instance, an address bus of \(n\) bits can address \(2^n\) unique memory locations.
2. The Data Bus
• Purpose: Carries the actual binary data or program instructions between the CPU, RAM, and I/O devices.
• Direction: Bidirectional (two-way; data can travel from RAM to CPU during a read, or from CPU to RAM during a write).
• Bus Width: The width (e.g., \(32\)-bit or \(64\)-bit) dictates how much data can be transferred in one single operation.
3. The Control Bus
• Purpose: Carries control and timing signals generated by the Control Unit to coordinate activities across the computer and avoid data collisions.
• Direction: Bidirectional (various control lines send commands and receive status signals).
• Common signals include:
- Memory Read (tells RAM to place data at the specified address onto the data bus)
- Memory Write (tells RAM to save the value on the data bus into the specified address)
- Bus Request & Bus Grant (negotiates access to the bus)
- Clock Pulses (synchronizes operations)
- Interrupt Requests (alerts CPU that a device needs urgent attention)
Quick Summary Table:
• Address Bus: Unidirectional | Carries physical memory addresses
• Data Bus: Bidirectional | Carries actual program instructions & values
• Control Bus: Bidirectional | Carries control, status, and synchronization signals
4. The Fetch-Decode-Execute (F-D-E) Cycle
The core purpose of the CPU is to run programs by continuously repeating the Fetch-Decode-Execute Cycle from the moment you turn on the computer until it shuts down.
Step 1: The Fetch Stage
The CPU retrieves an instruction from primary memory (RAM):
1. The address of the next instruction is copied from the Program Counter (PC) to the Memory Address Register (MAR).
2. The address is sent along the Address Bus to RAM.
3. The Control Unit sends a Memory Read control signal along the Control Bus.
4. RAM locates the contents at that address and sends the instruction across the Data Bus into the Memory Data Register (MDR).
5. The instruction in the MDR is copied to the Current Instruction Register (CIR) for decoding.
6. Simultaneously, the Program Counter (PC) increments by \(1\) (\(PC = PC + 1\)), pointing to the next instruction in sequence.
Step 2: The Decode Stage
The Control Unit inspects the instruction held in the CIR:
1. The instruction is split into two parts: the Opcode (the operation code, e.g., ADD, SUB, LOAD, STORE) and the Operand (the address or data value to be operated on).
2. The Control Unit's internal decoder determines exactly what circuitry needs to be activated.
Step 3: The Execute Stage
The instruction is carried out:
• If data needs to be fetched from memory, the address part of the instruction is sent to the MAR.
• If an arithmetic or logic operation is required, the ALU performs the calculation and saves the output in the Accumulator (ACC).
• If the instruction is a jump/branch, the PC is updated with a new target address.
• Once complete, the cycle immediately restarts at Step 1!
Common Student Mistake:
Mistake: Thinking the PC increments during the execute stage.
Correction: The PC increments during the fetch stage, right after the current address has been passed to the MAR. This ensures it is ready for the next cycle.
5. Factors Affecting CPU Performance
Why is one processor faster than another? CPU performance is governed by several core hardware characteristics working in harmony.
1. Clock Speed
The CPU contains an internal quartz crystal clock. With every tick of this clock, a single step in a CPU operation can occur.
• Measurement: Measured in Hertz (Hz), where \(1\text{ Hz} = 1\text{ cycle per second}\). Modern CPUs are measured in Gigahertz (GHz), where \(1\text{ GHz} = 1\text{ billion cycles per second}\).
• Impact: A higher clock speed means more fetch-decode-execute cycles can be completed per second, resulting in faster program execution.
• Limitation: Increasing clock speed generates excessive heat and consumes more electrical power (requiring sophisticated cooling systems).
2. Cache Memory Size and Levels
Cache is a small amount of extremely high-speed static RAM (SRAM) built directly onto or right beside the CPU chip.
• How it works: Accessing standard RAM takes many CPU clock cycles. Cache stores frequently used instructions and data so the CPU doesn't have to wait for slower RAM transfers.
• Cache Levels:
- Level 1 (L1) Cache: Smallest capacity (\(32\text{ KB} - 128\text{ KB}\)), but located directly on the processor core; extremely fast.
- Level 2 (L2) Cache: Larger than L1, slightly slower, dedicated to each core.
- Level 3 (L3) Cache: Largest capacity (several megabytes), shared across all cores, slower than L1/L2 but still significantly faster than main RAM.
• Impact: More cache means a higher "cache hit rate" (finding needed data in cache instead of having to fetch from RAM), minimizing processor idle time.
3. Number of Processor Cores
A core is a complete, independent processing unit containing its own CU, ALU, and registers.
• Single-core: Can only process one instruction at any single moment.
• Multi-core (Dual-core, Quad-core, Octa-core): A dual-core CPU has \(2\) processing cores; a quad-core has \(4\) processing cores. They can execute multiple instructions simultaneously (known as parallel processing).
• Important Exam Note: Doubling the number of cores does not automatically double performance! Software must be written specifically for multi-threading to take advantage of multiple cores. Additionally, cores must spend time coordinating and sharing data via buses, creating overhead.
4. Bus Width
• Data Bus Width: If the data bus width increases from \(32\)-bit to \(64\)-bit, the CPU can transfer twice as much data in a single cycle between memory and the processor.
• Address Bus Width: Determines the maximum addressable memory capacity. A CPU with a \(32\)-bit address bus can address up to \(2^{32}\text{ bytes} = 4\text{ Gigabytes (GB)}\) of RAM, whereas a \(64\)-bit address bus can address \(2^{64}\text{ bytes}\) (vastly more memory).
Chapter Summary & Quick Review
Quick Check Checklist:
• Von Neumann Architecture: Instructions and data share the same memory space and buses.
• Control Unit (CU): Manages execution, decodes instructions, and issues control signals.
• Arithmetic Logic Unit (ALU): Performs mathematical calculations and logical comparisons.
• Registers: Ultra-fast CPU memory (PC \(\rightarrow\) MAR \(\rightarrow\) MDR \(\rightarrow\) CIR \(\rightarrow\) ACC).
• Buses: Address Bus (unidirectional), Data Bus (bidirectional), Control Bus (bidirectional).
• F-D-E Cycle: Fetch instruction from RAM \(\rightarrow\) Decode in CIR \(\rightarrow\) Execute via ALU/CU \(\rightarrow\) Repeat.
• Performance Factors: Clock speed, Cache memory size/levels, Number of cores, and Bus width.