Introduction to Computer Architecture
Welcome to Computer Architecture! Have you ever wondered what actually happens inside a computer when you click a mouse, open an app, or run a program? Inside the processor, millions of lightning-fast calculations and data transfers happen every single second.
In this chapter from AS 2: Fundamentals of Digital Technology, we will explore the internal layout of the computer, how the processor retrieves and runs instructions, and what makes some computers faster than others. Don't worry if this seems complex at first—we will break down each concept step by step with everyday analogies to make everything clear and memorable!
1. CPU Architectures: Von Neumann vs. Harvard
The Central Processing Unit (CPU) is often called the "brain" of the computer. It is responsible for fetching instructions, decoding them, and executing them. However, computers can be designed with different internal structural models.
The Von Neumann Architecture
In 1945, mathematician John von Neumann introduced the Stored Program Concept. In a Von Neumann architecture:
• Data and instructions share the same physical memory (Random Access Memory / RAM).
• Data and instructions travel along the same shared buses (data pathways).
• Instructions are executed sequentially (one after another).
Analogy: Imagine a single one-lane bridge connecting two towns. Both delivery trucks (data) and construction workers with blueprints (instructions) have to share that single lane. Because only one can cross at a time, traffic can slow down.
The Von Neumann Bottleneck: Because instructions and data must wait to use the same bus, the CPU frequently has to wait for data to be transferred to or from memory. The overall processing speed is limited by the data transfer rate of the bus system.
The Harvard Architecture
In the Harvard architecture:
• Data and instructions are kept in physically separate memories.
• Separate sets of buses are used for data and instructions.
• This allows the CPU to fetch a new instruction at the exact same time it reads or writes data in memory!
Analogy: Imagine having two completely separate bridges: one bridge exclusively for trucks carrying goods (data) and another bridge strictly for engineers carrying instruction manuals (instructions). Both can cross simultaneously without getting in each other's way.
Where is Harvard used? It is widely used in Digital Signal Processors (DSPs), audio/video processing chips, and embedded microcontrollers where high-speed predictable processing is required.
Quick Comparison
• Von Neumann: Simpler design, cheaper to build, uses memory space efficiently, but suffers from the shared bus bottleneck.
• Harvard: Faster throughput because data and instructions are accessed at the same time, but more complex and expensive to manufacture.
Key Takeaway: Von Neumann uses one shared memory and bus for both data and code (leading to a bottleneck), whereas Harvard uses separate memories and buses for each.
2. Internal Components of the CPU
The CPU is made up of three main sections: the Control Unit (CU), the Arithmetic Logic Unit (ALU), and dedicated temporary storage areas called Registers.
The Control Unit (CU)
The Control Unit acts as the conductor of an orchestra. It does not perform calculations itself; instead, it coordinates and directs all operations within the CPU by:
• Managing the Fetch-Decode-Execute cycle.
• Decoding instructions.
• Sending out electrical control and timing signals to synchronize operations across the whole system.
The Arithmetic Logic Unit (ALU)
The ALU is the computer's internal calculator. It handles two types of operations:
• Arithmetic operations: Mathematical calculations like addition (\(+\)), subtraction (\(-\)), multiplication (\(\times\)), and division (\(\div\)).
• Logical operations: Comparisons and Boolean evaluations such as \(AND\), \(OR\), \(NOT\), and checking whether one value is greater than, less than, or equal to another (\(>\), \(<\), \(=\)).
Internal Registers
Registers are extremely small, ultra-fast memory cells located directly on the CPU chip. They hold temporary values needed during processing.
Here are the 5 core registers you need to know for your exam:
1. Program Counter (PC): Holds the memory address of the next instruction waiting to be fetched and executed. It increments by 1 automatically after every fetch.
2. Memory Address Register (MAR): Holds the address in RAM that is currently being accessed (either for reading an instruction/data or writing data back to memory).
3. Memory Data Register (MDR) (also known as the Memory Buffer Register): Holds the actual data or instruction that has just been read from memory, or is waiting to be written to memory.
4. Current Instruction Register (CIR): Holds the instruction that has just been fetched and is currently being decoded and executed. It splits instructions into the Opcode (what operation to do) and the Operand (what data/address to do it on).
5. Accumulator (ACC): A temporary working register that holds the results of calculations performed by the ALU.
Memory Trick:
• Program Counter = Points to the Coming next instruction.
• Memory Address Register = Always holds an Address.
• Memory Data Register = Directly holds the Data.
Key Takeaway: The CU directs traffic, the ALU does the math/logic, and the registers act as high-speed scratchpads for addresses and intermediate values.
3. System Buses
A bus is a set of parallel electrical tracks or wires connecting the CPU to memory and other hardware devices. Together, these are known as the System Bus.
The Address Bus
• Purpose: Carries memory addresses from the CPU to the RAM.
• Direction: Unidirectional (one-way only). Addresses only travel from the CPU to the memory or input/output controllers.
• Bus Width: The number of parallel lines determines how many unique memory locations the CPU can address. A bus with \(n\) lines can address \(2^n\) distinct memory locations. For example, a 32-bit address bus can access \(2^{32} = 4\text{ GB}\) of RAM.
The Data Bus
• Purpose: Carries the actual program instructions and raw data between the CPU, memory, and input/output controllers.
• Direction: Bidirectional (two-way). Data can travel to the CPU (reading) or away from the CPU (writing).
• Bus Width: Dictates the word size of the computer (how many bits can be transferred in a single operation, e.g., 32-bit or 64-bit).
The Control Bus
• Purpose: Transmits control and synchronization signals from the Control Unit to make sure different components do not clash or transmit data at the wrong time.
• Direction: Bidirectional (two-way), because the CPU both sends commands (e.g., Memory Read, Memory Write, Bus Grant) and receives signals (e.g., Interrupt Requests, Bus Requests, Clock pulses).
Common Exam Trap to Avoid: Students often state that all buses are bidirectional. Remember: the Address Bus is UNIDIRECTIONAL!
Key Takeaway: The Address bus points to where data is (one-way), the Data bus moves what is stored (two-way), and the Control bus tells hardware when and how to act (two-way).
4. The Fetch-Decode-Execute (FDE) Cycle
The FDE cycle is the continuous sequence of steps performed by the CPU to execute every single instruction in a program.
Step 1: The Fetch Phase
1. The address stored in the Program Counter (PC) is copied to the Memory Address Register (MAR).
2. The Program Counter (PC) is incremented by 1 (\(PC \leftarrow PC + 1\)) so it points to the next instruction in sequence.
3. The CU sends a Read command down the Control Bus, and the address is sent along the Address Bus to RAM.
4. The contents stored at that address in memory travel across the Data Bus into the Memory Data Register (MDR).
5. The instruction in the MDR is copied to the Current Instruction Register (CIR).
Step 2: The Decode Phase
1. The Control Unit (CU) examines the instruction inside the CIR.
2. The instruction is split into:
• Opcode: The operation code specifying what action to take (e.g., ADD, SUB, STORE).
• Operand: The data or memory address upon which the operation should be performed.
3. The CU decodes the opcode into hardware signals ready for execution.
Step 3: The Execute Phase
1. The decoded instruction is carried out.
2. If data is needed from memory, it is fetched into the MDR.
3. If an arithmetic calculation or logic check is required, the ALU performs it and saves the output to the Accumulator (ACC).
4. If a jump/branch instruction occurs, the PC is updated with a new target address.
5. The cycle repeats from Step 1!
Key Takeaway: Fetch brings the instruction from RAM into the CPU, Decode works out what needs to be done, and Execute carries out the instruction.
5. Factors Affecting CPU Performance
Why is a modern high-end processor faster than an older one? Processing power is determined by several interrelated hardware factors:
1. Clock Speed
• The CPU contains an internal quartz crystal clock that pulses at a steady frequency.
• Each tick of the clock represents a clock cycle. In general, one operation (or stage of the FDE cycle) takes place per cycle.
• Measured in Gigahertz (GHz). A \(3.5\text{ GHz}\) CPU generates \(3.5 \text{ billion}\) clock pulses per second!
• Effect: A higher clock speed allows more instructions to be fetched and processed per second.
2. Cache Memory
• Cache is a small amount of extremely fast Static RAM (SRAM) built directly into or right beside the CPU core.
• It stores frequently and recently used instructions and data so the CPU doesn't have to wait for the much slower main memory (RAM).
• Level 1 (L1) is tiny but fastest; Level 2 (L2) and Level 3 (L3) are progressively larger but slightly slower.
• Effect: Larger cache sizes mean fewer requests to main RAM, reducing latency and avoiding the Von Neumann bottleneck.
3. Number of Processor Cores
• A core is a complete, independent processing unit containing its own CU, ALU, and registers.
• A Dual-core processor has 2 cores, a Quad-core has 4, and an Octa-core has 8.
• Multiple cores allow parallel processing (running different instructions simultaneously) or multitasking (running separate applications simultaneously).
• Limitation: Doubling the number of cores does not automatically double performance! Software must be written specifically to take advantage of parallel cores, and coordination overheads (inter-core communication) can reduce efficiency.
4. Bus Width
• Data Bus Width: A wider data bus (e.g., 64-bit vs 32-bit) can transfer more data in a single clock pulse, boosting data throughput.
• Address Bus Width: Determines the maximum amount of addressable physical RAM. A system with a 32-bit address bus is limited to \(2^{32}\text{ bytes} = 4\text{ GB}\) of RAM, whereas a 64-bit bus can address millions of terabytes.
Key Takeaway: CPU performance is a balancing act between clock speed, cache size, number of active cores, and bus width.
6. Interrupts and Interrupt Handling
What happens if a printer runs out of paper, or you press a key on your keyboard while the CPU is in the middle of executing a program? The CPU needs a way to be alerted!
What is an Interrupt?
An interrupt is a signal sent by hardware or software to the CPU, asking for its immediate attention and pausing the currently running process.
• Hardware Interrupt: Generated by physical hardware devices (e.g., mouse click, keypress, printer out of ink, power supply failure).
• Software Interrupt: Generated by programs requesting operating system services or flagging errors (e.g., divide by zero, file not found).
The Interrupt Handling Process (Step-by-Step)
When an interrupt signal is received during an FDE cycle:
1. The CPU finishes executing the current instruction in the FDE cycle.
2. The CPU checks the priority of the interrupt against any current tasks.
3. If the interrupt has higher priority, the CPU suspends the current program.
4. The contents of all CPU registers (the current execution state) are saved onto a special memory structure called the Stack.
5. The Program Counter (PC) is loaded with the start address of the Interrupt Service Routine (ISR) (a dedicated mini-program designed to handle that specific event).
6. The ISR executes to resolve the interrupt (e.g., reading the keystroke).
7. Once finished, the previous state of the CPU is popped off the Stack and restored into the registers.
8. The CPU resumes its original program exactly where it left off.
Analogy: Imagine you are reading a book (the main program). The doorbell rings (an interrupt). You don't drop everything instantly mid-word; you finish reading the current sentence, place a bookmark in the book to save your exact page and line (saving to the stack), answer the door (the ISR), and once the guest is greeted, you open the book back at the bookmark and continue reading peacefully.
Key Takeaway: Interrupts temporarily halt normal processing. The CPU safely preserves its state on the stack, executes the ISR, and then restores its state to continue working.
Quick Review Checklist
Before moving on to the next topic, make sure you can answer these questions confidently:
• Can you describe the difference between the Von Neumann and Harvard architectures?
• Can you list the 5 key registers (PC, MAR, MDR, CIR, ACC) and explain what each one stores?
• Which bus is unidirectional, and which two are bidirectional?
• What are the precise register transfers that happen during the Fetch phase?
• Why doesn't doubling the number of CPU cores automatically double a computer's overall speed?
• What role does the Stack play during interrupt handling?