Hardware and Virtual Machines: Practice Questions

In digital logic, which gate is defined as producing a logic high (1) output if and only if the two binary inputs are different?

In Virtual Machine architecture, what is the specific function of the hypervisor?

In Flynn’s Taxonomy of computer architectures, which category is most commonly associated with a Graphics Processing Unit (GPU) designed to perform the same calculation on a large block of pixels simultaneously?

According to Flynn's Taxonomy of computer architectures, which classification represents a traditional von Neumann machine where a single stream of instructions operates on a single stream of data?

Using De Morgan’s Laws, simplify the following Boolean expression to its most basic form:
\( \overline{\overline{A \cdot B} + C} \)

State the input condition for an SR flip-flop (using NOR gates) that results in an invalid or forbidden state.

Identify which of Flynn’s Taxonomy architectures is represented by a multi-core processor system where each core independently executes different instruction streams on different data streams, and justify your answer.

Describe how a JK Flip-flop overcomes the "invalid" or "forbidden" state inherent in a basic SR Flip-flop when both inputs are set to logic 1.

A logic storage circuit can be constructed using flip-flops.
(a) State the main difference between an SR flip-flop and a JK flip-flop when both inputs are set to binary 1.
(b) State the logic values of the outputs \( Q \) and \( \overline{Q} \) of an SR flip-flop when it is in the Set state.
(c) Explain why flip-flops are essential components in the design of computer hardware registers.

Hardware and Virtual Machines processors are often categorized into two main design philosophies: RISC and CISC.
(a) Identify two characteristics of a CISC processor that distinguish it from a RISC processor.
(b) Pipelining is a common feature in modern processors. Explain how the uniform instruction length of a RISC processor makes the implementation of pipelining more efficient compared to a CISC processor.