Basic Machine Organisation: Practice Questions

During the 'fetch' stage of the CPU's instruction cycle, from which hardware component does the CPU retrieve the next command?

Consider the following components of a CPU:
I. Arithmetic and Logic Unit (ALU)
II. Control Unit (CU)
III. Instruction Register (IR)
IV. Program Counter (PC)
During the decode stage of the machine cycle, which components are primarily active in interpreting the instruction and coordinating the next steps?

A computer system utilizes a 24-bit address bus and the memory is byte-addressable. During the fetch stage of the machine cycle, the Program Counter (PC) is incremented after the instruction is sent to the Instruction Register (IR). If each instruction is 4 bytes long and the current instruction was fetched from address \(0x00A000\), what is the maximum physical memory capacity of this system and what is the new value in the PC?

During the 'fetch' stage, in which register is the instruction itself temporarily stored once it is retrieved from memory?

Consider the following sequence of events during the execute phase of an instruction that performs an addition between a register and a memory operand: ADD R1, [500]. Which of the following describes the correct status of the Address Bus and Data Bus during the sub-cycle where the operand is retrieved?

State the fundamental difference between Random Access Memory (RAM) and Read-Only Memory (ROM) concerning the volatility of their stored data.

A Central Processing Unit (CPU) with a 64-bit word length is operating within a system where the data bus connecting the CPU to the main memory (RAM) is only 32 bits wide, while the address bus is 48 bits wide. Analyze the implications of the 32-bit data bus limitation on the fetch phase of a single 64-bit instruction, specifically describing the number of main memory access cycles required to retrieve the instruction and the specific register responsible for ensuring the complete 64-bit instruction is assembled before decoding.

Primary storage is essential for a computer system's operation, and it commonly includes Random Access Memory (RAM) and Read-Only Memory (ROM).

(a) State two fundamental differences between RAM and ROM based on their functional characteristics. (2 points)

(b) The maximum physical memory that a Central Processing Unit (CPU) can directly address is determined by the width of its address bus.

If a computer system has an address bus that is 20 bits wide, calculate the maximum memory capacity, in kilobytes (KB), that the CPU can address.

(Assume 1 Kilobyte (KB) = \(2^{10}\) Bytes.) (2 points)

A microcontroller unit (MCU) used in an advanced IoT device features a Central Processing Unit (CPU) architecture with a 64-bit word length. The hardware design imposes certain constraints on the bus system and memory management.

(a) Memory Addressing Capacity

The MCU utilizes an address bus that is 38 bits wide.

i. Calculate the maximum amount of physical memory, in Gigabytes (GB), that the CPU can directly address. Show your steps. (Assume \(1 \text{ GB} = 2^{30} \text{ Bytes}\)). (2 points)

(b) Data Transfer Efficiency

While the CPU has a 64-bit word length, the data bus connecting the CPU to the main memory (RAM) is only 32 bits wide.

i. Explain the process by which a single 64-bit instruction is transferred from the RAM to the CPU registers during the fetch phase, explicitly mentioning the number of memory access cycles required due to the data bus width limitation. (2 points)