AS 5 Material Science: Semiconductors
Welcome to your study notes for Section 5.8: Semiconductors of the CCEA AS Life and Health Sciences specification (Unit AS 5: Material Science). Don't worry if physics and material structures have felt tricky before—we will break down every single concept step-by-step so that you can tackle your exam with complete confidence!
---1. Electrical Conduction and Band Theory
To understand how semiconductors work, we first look at how electrons behave inside solid crystal structures.
What is an Intrinsic Semiconductor?
An intrinsic semiconductor is a pure semiconductor material containing no intentional impurity atoms. The standard examples in Group IV of the Periodic Table are pure Silicon (\(\text{Si}\)) and pure Germanium (\(\text{Ge}\)).
Energy Band Theory
In solid materials, electron energy levels merge into bands. Conduction is explained by three key zones:
• Valence Band: The highest occupied energy band where electrons are tightly bound to atoms at absolute zero.
• Conduction Band: The higher energy band where electrons have gained enough energy to break free from covalent bonds and move freely through the lattice to conduct electricity.
• Forbidden Energy Gap (\(E_g\)): The energy difference between the top of the valence band and the bottom of the conduction band. Electrons cannot exist within this gap. Semiconductors have a relatively narrow band gap compared to electrical insulators.
Charge Carriers in Pure Semiconductors
Unlike metals (which conduct only via free electrons), semiconductors have two types of mobile charge carriers:
1. Free Electrons: Negatively charged carriers that have gained enough thermal energy to jump into the conduction band.
2. Holes: When an electron jumps into the conduction band, it leaves behind an empty space in the valence band. This positive vacancy is called a hole. A neighbouring valence electron can step into this vacancy, effectively moving the positive hole through the crystal lattice.
Temperature and Resistance
Did you know? Intrinsic semiconductors behave very differently from standard metals when heated.
• In metals, heating increases lattice vibrations, causing resistance to increase.
• In intrinsic semiconductors, heating provides thermal energy that breaks covalent bonds, creating many new electron-hole pairs. Because so many extra charge carriers are released, their electrical conductivity increases and their electrical resistance decreases.
• Therefore, intrinsic semiconductors have a negative temperature coefficient of resistance.
Key Takeaway for Section 1: Pure (intrinsic) semiconductors like \(\text{Si}\) and \(\text{Ge}\) conduct electricity via both free electrons in the conduction band and positive holes in the valence band across a narrow forbidden energy gap (\(E_g\)).
---2. Doping and Extrinsic Semiconductors
Pure silicon is only a weak conductor at room temperature. To make useful electronic devices, scientists modify its conductivity through a process called doping.
What is Doping?
Doping is the deliberate addition of tiny, controlled amounts of specific impurity atoms into the pure semiconductor crystal lattice to dramatically increase its electrical conductivity. A semiconductor that has been doped is known as an extrinsic semiconductor.
n-type Semiconductors
• Impurity Used: Doped with pentavalent impurity atoms (Group V elements such as Phosphorus, \(\text{P}\), or Arsenic, \(\text{As}\)).
• How it works: The pentavalent atom has \(5\) valence electrons. It uses \(4\) electrons to form covalent bonds with neighbouring silicon atoms, leaving the \(5^{\text{th}}\) electron loosely bound. This extra electron easily enters the conduction band as a "donor" electron.
• Majority Charge Carriers: Free electrons.
• Minority Charge Carriers: Thermally generated holes.
p-type Semiconductors
• Impurity Used: Doped with trivalent impurity atoms (Group III elements such as Boron, \(\text{B}\), or Gallium, \(\text{Ga}\)).
• How it works: The trivalent atom has only \(3\) valence electrons. When fitting into the crystal lattice, it can only form \(3\) complete covalent bonds. This leaves a vacancy or "hole" that readily accepts an electron from an adjacent bond.
• Majority Charge Carriers: Holes (positive vacancies).
• Minority Charge Carriers: Thermally generated free electrons.
Memory Aid: Remembering n-type vs. p-type
• n-type: Negative majority carriers (free electrons) \(\rightarrow\) Group V (Pentavalent donor).
• p-type: Positive majority carriers (holes) \(\rightarrow\) Group III (Trivalent acceptor).
Examiner Warning: Net Electrical Neutrality
A classic exam mistake is believing that an n-type piece of silicon is negatively charged overall, or that a p-type piece is positively charged overall. This is false! Both n-type and p-type semiconductors remain electrically neutral as a whole, because the total number of protons in the atomic nuclei exactly balances the total number of orbital electrons.
Key Takeaway for Section 2: Adding Group V atoms creates n-type material (majority carriers = electrons), while adding Group III atoms creates p-type material (majority carriers = holes). Both materials remain electrically neutral.
---3. The p-n Junction & Depletion Layer
When a p-type region and an n-type region meet within a single, continuous crystal, they form a p-n junction—the fundamental building block of semiconductor diodes and transistors.
Step-by-Step Formation of the Depletion Region
Step 1: Diffusion
At the boundary between the two regions, there is a large difference in carrier concentration. Free electrons from the n-side diffuse across the junction into the p-side, while holes from the p-side diffuse across into the n-side.
Step 2: Recombination
When these diffusing electrons meet holes near the junction, they recombine and cancel each other out as mobile charge carriers.
Step 3: Uncompensated Fixed Ions
• When donor atoms on the n-side lose their free electrons, they become immobile positively charged donor ions fixed in the lattice.
• When acceptor atoms on the p-side gain electrons, they become immobile negatively charged acceptor ions fixed in the lattice.
Step 4: The Depletion Region and Potential Barrier
The region close to the interface is now cleared ("depleted") of mobile charge carriers. This layer is called the depletion region. The fixed positive ions on the n-side and fixed negative ions on the p-side set up a built-in internal electric field pointing from the n-side to the p-side. This electric field creates a potential barrier that opposes and eventually halts any further diffusion of majority carriers across the junction at equilibrium.
Key Takeaway for Section 3: The depletion layer contains no mobile charge carriers—only fixed positive donor ions on the n-side and fixed negative acceptor ions on the p-side, setting up a potential barrier that halts diffusion.
---4. Biasing the p-n Junction
Connecting an external direct current (\(\text{DC}\)) voltage supply to a p-n junction is called biasing. How the junction behaves depends entirely on the polarity of the connection.
Forward Bias
• Connection: The positive terminal of the power supply is connected to the p-type region, and the negative terminal is connected to the n-type region.
• Mechanism: The applied external voltage opposes the built-in potential barrier. Holes on the p-side and electrons on the n-side are repelled by the supply terminals toward the junction, which narrows the depletion region.
• Current Flow: Once the applied forward voltage overcomes the threshold voltage (approximately \(0.7\text{ V}\) for Silicon, \(\text{Si}\)), the potential barrier collapses and a large forward current flows easily.
Reverse Bias
• Connection: The positive terminal of the power supply is connected to the n-type region, and the negative terminal is connected to the p-type region.
• Mechanism: The positive terminal attracts majority electrons away from the junction on the n-side, and the negative terminal attracts majority holes away from the junction on the p-side. This widens the depletion region and increases the height of the potential barrier.
• Current Flow: Majority carriers cannot cross the barrier. Only a tiny, negligible reverse leakage current flows due to the drift of thermally generated minority carriers across the junction (until electrical breakdown occurs at very high voltages).
Quick Summary of Biasing Polarities
• Forward Bias: Positive to p-type, Negative to n-type \(\rightarrow\) Depletion region narrows \(\rightarrow\) Large current flows once \(V > 0.7\text{ V}\) (for \(\text{Si}\)).
• Reverse Bias: Positive to n-type, Negative to p-type \(\rightarrow\) Depletion region widens \(\rightarrow\) Extremely high resistance, negligible current.
Key Takeaway for Section 4: A p-n junction acts as a one-way valve for electric current: it conducts heavily under forward bias once threshold voltage is reached, but blocks current under reverse bias.
---5. Quick Review & Exam Pitfall Checklist
Before entering your AS 5 exam, review these common traps identified by examiners:
• Mistake 1: Overall Charge of Doped Materials: Remember that n-type and p-type semiconductors are electrically neutral. An n-type material has extra free electrons, but it also has an equal number of positive nuclear protons in its donor atoms.
• Mistake 2: Diffusion vs. Drift: Diffusion is the movement of majority carriers down their concentration gradient across the junction. Drift is the movement of minority carriers driven by the internal or external electric field.
• Mistake 3: Temperature Effects: Unlike metals, intrinsic semiconductors have a negative temperature coefficient of resistance because thermal energy breaks bonds to generate more electron-hole pairs, lowering the overall resistance.
• Mistake 4: Biasing Connections: Double-check your circuit diagrams! Forward bias requires Positive to p-type and Negative to n-type.