Processor Fundamentals：練習題

Which component of the Central Processing Unit (CPU) is responsible for decoding instructions and generating control signals to manage the flow of data between the processor and other components?

During the Fetch-Execute cycle, which of the following Register Transfer Notations (RTN) correctly represents the step where the instruction is retrieved from memory and placed into the Memory Data Register (MDR)?

When an interrupt is detected by the CPU at the end of a Fetch-Execute cycle, what is the first critical action the processor must take before loading the address of the Interrupt Service Routine (ISR) into the Program Counter (PC)?

In the Von Neumann architecture, which special purpose register is responsible for holding the memory address of the next instruction to be fetched?

An 8-bit accumulator (ACC) contains the binary value \( 00001101 \). If the assembly language instruction LSL #2 (Logical Shift Left by 2 places) is executed, what will be the resulting denary value in the accumulator?

Describe the steps involved in the Fetch stage of the Fetch-Execute cycle, specifically mentioning the registers involved and their roles.

A processor is executing a program. An interrupt occurs during the execution of an instruction.

(a) Describe the sequence of events that the processor follows to handle an interrupt, starting from when the interrupt is detected until the execution of the interrupted program is resumed. Your description should include the role of the Interrupt Service Routine (ISR) and the registers involved.

(b) The status of the current process is saved before the ISR is executed. Explain why it is necessary to save the Status Register specifically, in addition to the Program Counter (PC).

(c) In the Fetch-Execute cycle, at what point exactly is an interrupt signal checked? Justify why this specific timing is used.