Processor Fundamentals：練習題

During the Fetch-Execute cycle, what is the role of the Control Unit (CU) during the 'decode' stage?

A processor is described as having a 'Quad-core' architecture. How does increasing the number of cores generally affect performance?

During the two-pass assembly process of a program written in assembly language, which of the following tasks is carried out exclusively during the second pass?

Which of the following describes the function of the Address Bus in a processor?

What is the primary function of the Interrupt Service Routine (ISR)?

In the context of the Von Neumann model, state the stored program concept.

Compare the immediate addressing mode with the direct addressing mode in assembly language instructions.

Explain the exact sequence of steps taken by the processor when an interrupt is detected and handled at the end of the Fetch-Execute cycle.

In the Von Neumann model, the Central Processing Unit (CPU) uses several special purpose registers during the Fetch-Execute cycle.

(a) Describe the purpose of the Memory Address Register (MAR) and the Memory Data Register (MDR). [2]

(b) During the fetch stage of the cycle, the following register transfer occurs:
\( \text{MAR} \to [\text{memory}] \to \text{MDR} \)
Explain what is happening during this specific step. [1]

A programmer is writing a routine to manipulate bit-level data stored in the Accumulator (ACC). The current 8-bit binary value in the ACC is 1011 0011.

(a) Show the result of performing a logical left shift (LSL) by 2 places on the value 1011 0011. [1]

(b) The programmer wants to ensure that the 4 most significant bits of an 8-bit value are cleared (set to 0) while keeping the 4 least significant bits unchanged. Identify the logic operation (e.g., AND, OR, XOR) and the 8-bit mask required to achieve this. [2]

(c) Explain the difference between direct addressing and indirect addressing in the context of fetching an operand for an assembly instruction. [2]