Assembly language programming：练习题

Which of the following statements correctly distinguishes between assembly language and machine code?

Register R1 currently holds the value 15 and register R2 holds the value 10. Trace the following instructions:

ADD R1, R1, R2
SUB R1, R1, #3

What is the final value stored in R1?

Trace the following assembly code snippet to determine the final value in register R1:

MOV R1, #0
MOV R2, #3
loop:
ADD R1, R1, R2
SUB R2, R2, #1
CMP R2, #0
BNE loop

In the context of a processor's instruction set, which part of an assembly language instruction specifies the actual operation to be performed by the CPU?

Which logical bitwise instruction and mask should be used to ensure that the least significant bit (bit 0) of an 8-bit value in register R1 is set to 0, while all other bits remain unchanged?

Define the term immediate addressing as it is used within an assembly language instruction format.

Contrast direct addressing and indirect addressing by explaining how the processor identifies the data to be operated on in each mode.

A programmer uses a logical shift left operation by 3 places on an 8-bit register containing the value \( 00000101_2 \).
State the resulting bit pattern and explain the mathematical effect this has on the original denary value.

Assembly language is a low-level programming language that uses mnemonics to represent machine code instructions specific to a processor.

(a) Define the term instruction set.
(b) Describe the difference between immediate addressing and direct addressing.
(c) Identify the opcode and the operand in the following assembly instruction:
LDR \(R1\), 100

A programmer is required to convert a high-level selection structure into assembly language for the OxfordAQA processor.

(a) Write the equivalent assembly language code for the following pseudocode:
IF (\(R1\) > \(R2\)) THEN
    \(R1\) = \(R1\) - \(R2\)
ENDIF

(b) Explain how indirect addressing is used in an instruction such as LDR \(R1\), [\(R2\)].
(c) Describe how the Status Register (SR) is involved in the execution of the CMP and conditional branch instructions used in your answer to part (a).